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LTC3207/LTC3207-1
OPERATION
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave (LTC3207/LTC3207-1) lets the mas-
ter know that the latest byte of information was received.
The Acknowledge-related clock pulse is generated by the
master. The master releases the SDA line (HIGH) during
the Acknowledge clock cycle. The slave-receiver must pull
down the SDA line during the Acknowledge clock pulse
so that it remains a stable LOW during the HIGH period
of this clock pulse.
Slave Address
The LTC3207 responds to only one 7-bit address which
has been factory programmed to 0011011. The LTC3207-1
responds to only one 7-bit address which has been factory
programmed to 0011010. The eighth bit of the address
byte (R/W) must be 0 for the LTC3207/LTC3207-1 to
recognize the address since it is a write-only device. This
effectively forces the address to be 8 bits long where the
least signi?cant bit of the address is 0. If the correct seven
bit address is given but the R/W bit is 1, the LTC3207/
LTC3207-1 will not respond.
Bus Write Operation
The master initiates communication with the LTC3207/
LTC3207-1 with a START condition and a 7-bit address
followed by the write bit R/W = 0. If the address matches
that of the LTC3207/LTC3207-1, the device returns an
Acknowledge. The master should then deliver the most
signi?cant sub-address byte for the data register to be
written. Again, the LTC3207/LTC3207-1 acknowledge
and then the data is delivered starting with the most sig-
ni?cant bit. This cycle is repeated until all of the required
data registers have been written. Any number of data
registers can be written. Each data byte is transferred to
an internal holding latch upon the return of an Acknowl-
edge. After all data bytes have been transferred to the
LTC3207/LTC3207-1, the master may terminate the
communication with a STOP condition. Alternatively, a
REPEAT-START condition can be initiated by the master
and another chip on the I 2 C bus can be addressed. This
cycle can continue inde?nitely and the LTC3207/LTC3207-1
will remember the last input of valid data that they receive.
Once all chips on the bus have been addressed and sent
valid data, a global STOP condition can be sent and the
LTC3207/LTC3207-1 will update all registers with the data
that it had received.
In certain circumstances the data on the I 2 C bus may become
corrupt. In these cases the LTC3207/LTC3207-1 respond
appropriately by preserving only the last set of complete
data that they have received. For example, assume the
LTC3207/LTC3207-1 have been successfully addressed
and are receiving data when a STOP condition mistakenly
occurs. The LTC3207/LTC3207-1 will ignore this stop
condition and will not respond until a new START condi-
tion, correct address, sub-address and new set of data
and STOP condition are transmitted.
Likewise, if the LTC3207/LTC3207-1 were previously ad-
dressed and sent valid data but not updated with a STOP,
they will respond to any STOP that appears on the bus
with only one exception, independent of the number of
REPEAT-STARTs that have occurred. If a REPEAT-START is
given and the LTC3207/LTC3207-1 successfully acknowl-
edge their address and ?rst byte, they will not respond to
a STOP until all bytes of the new data have been received
and acknowledged.
Quick Write
Registers REG1 to REG12 can be written in parallel by set-
ting Bit 1 of REG0 high. When this bit is set high the next
write sequence to REG1 will write the data to REG1 through
REG12 which is all of the universal LED registers.
3207fc
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